Papers - WEN Xiaoqing
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Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns Reviewed International journal
H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen
IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011.05
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Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme Reviewed International journal
F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed
IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011.05
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Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing Reviewed International journal
X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, M. Tehranipoor
IEEE VLSI Test Symposium 166 - 171 2011.05
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Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing Reviewed International journal
F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed
6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era 1 - 6 2011.04
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A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing Reviewed International journal
IEICE Transactions on Information and Systems E94-D ( 4 ) 833 - 840 2011.04
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Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation Reviewed International journal
K. Miyase, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara
Design, Automation and Test in Europe 895 - 898 2011.03
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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal
S. Wu,L.-T. Wang,X. Wen,Z. Jiang,M. Hsiao,W.-B. Jone,L. Tan,Y. Zhang,Y. Hu,C.-M. Li,Member,J.-L. Huang,L. Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30 ( 3 ) 455 - 463 2011.03
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X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme Reviewed International journal
K. Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara
IEEE Workshop on RTL and High Level Testing 125 - 129 2010.12
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Hybrid Memory Built-In Self-Test Architecture for Multi-port Static RAMs Reviewed International journal
L. Yu, J. Hung, B. Sheu, B. Huynh, L. Nguyen, S. Wu, L.-T. Wang, X. Wen
IEEE Int Symposium on Defect and Fault Tolerance in VLSI Systems 331 - 339 2010.11
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Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver Reviewed International journal
K. Miyase,M. A. Kochte,X. Wen,S. Kajihara,H.-J. Wunderlich
IEEE Workshop on Defect and Date Driven Testing 4 Pages 2010.11
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Is Test Power Reduction Through X-Filling Good Enough? Reviewed International journal
F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed
IEEE International Test Conference 805 - 805 Poster 2010.11
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On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test Reviewed International journal
S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, X. Wen
10th International Symposium on Communications and Information Technologies 723 - 726 2010.10
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Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains Reviewed International journal
S. Wu,L.-T. Wang,L. Yu,H. Furukawa,X. Wen,W.-B. Jone,N. A. Touba,F. Zhao,J. Liu,H.-J. Chao,F. Li,Z. Jiang
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 358 - 366 2010.10
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Case Studies on Transition Fault Test Generation for At-Speed Scan Testing Reviewed International journal
N. A. Zakariz, E. V. Bautista, S. M. Jusoh, W. F. Lee, X. Wen
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 180 - 188 2010.10
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A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes Reviewed International journal
F. Wu,L. Dilillo,A. Bosio,P. Girard,S. Pravossoudovitch,A. Virazel,M. Tehranipoor,X. Wen,N. Ahmed
ASP Journal of Lower Power Electronics 6 ( 2 ) 359 - 374 2010.08
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On Delay Test Quality for Test Cubes Reviewed International journal
S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen
IPSJ Transactions on System LSI Design Methodology 3 283 - 291 2010.08
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A Study of Capture-Safe Test Generation Flow for At-Speed Testing Reviewed International journal
K. Miyase, X. Wen, S. Kajihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja
IEICE Transactions on Information and Systems E93-A ( 7 ) 1309 - 1318 2010.07
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On Estimation of NBTI-Induced Delay Degradation Reviewed International journal
M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura
IEEE European Test Symposium 107 - 111 2010.05
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Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes Reviewed International journal
F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, X. Wen
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 376 - 381 2010.04
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High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Reviewed International journal
K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L. Wang, M. Tehranipoor
IEICE Transactions on Information and Systems E93-D ( 1 ) 2 - 9 2010.04