Faculty Profiles - WEN Xiaoqing

Papers - WEN Xiaoqing

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On Optimal Power-Aware Path Sensitization Reviewed International journal

Workshop of Test and Reliability for Circuits and Systems 2017.03

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding Reviewed International journal

Xiang D., Wen X., Wang L.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 ( 3 ) 942 - 953 2017.03

Vernier ring based pre-bond through silicon vias test in 3D ICs Reviewed International journal

Ni Tianming, Nie Mu, Liang Huaguo, Bian Jingchang, Xu Xiumin, Fang Xiangsheng, Huang Zhengfeng, Wen Xiaoqing

IEICE Electronics Express ( The Institute of Electronics, Information and Communication Engineers ) 14 ( 18 ) 20170590 - 20170590 2017.01

Language：English Publishing type：Research paper (scientific journal)

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.

DOI： 10.1587/elex.14.20170590

Scopus

CiNii Article

CiNii Research

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85030178580&origin=inward

Logic-Path-and-Clock-Path-Aware at-Speed Scan Test Generation Reviewed International journal

F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara

2016.12

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Reviewed International journal

LI Fuqiang, WEN Xiaoqing, MIYASE Kohei, HOLST Stefan, KAJIHARA Seiji

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( The Institute of Electronics, Information and Communication Engineers ) E99A ( 12 ) 2310 - 2319 2016.12

Language：English Publishing type：Research paper (international conference proceedings)

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power-safety without significant test vector count inflation and test quality loss.

DOI： 10.1587/transfun.E99.A.2310

Scopus

CiNii Article

CiNii Research

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84999232940&origin=inward

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST Reviewed International journal

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Asian Test Symposium 203 - 208 2016.11

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed International journal

Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.

IEEE Asian Test Symposium 19 - 24 2016.11

On Optimal Power-Aware Path Sensitization Reviewed International journal

Sauer M., Jiang J., Reimer S., Miyase K., Wen X., Becker B., Polian I.

IEEE Asian Test Symposium 179 - 184 2016.11

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test Reviewed International journal

Eggersglub S., Holst S., Tille D., Miyase K., Wen X.

Proceedings of the Asian Test Symposium 173 - 178 2016.11

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures Reviewed International journal

CHEN Tian, SHEN Dandan, YI Xin, LIANG Huaguo, WEN Xiaoqing, WANG Wei

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E99D ( 11 ) 2672 - 2681 2016.11

Language：English Publishing type：Research paper (scientific journal)

Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, X-filling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

DOI： 10.1587/transinf.2015EDP7289

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84994577136&origin=inward

Power-Aware Testing For Low-Power VLSI Circuits Invited Reviewed International journal

X. Wen

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings 585 - 588 Paper S37-1 2016.10

Authorship：Corresponding author Language：English Publishing type：Research paper (international conference proceedings)

China Hangzhou 2016.10.25 - 2016.10.28

DOI： 10.1109/ICSICT.2016.7998986

Kyutacar

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85028640934&origin=inward

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM Reviewed International journal

Syafalni I., Sasao T., Wen X.

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016-September 679 - 684 2016.07

SAT-Based Post-Processing for Regional Capture Power Reduction in at-speed scan test generation Reviewed International journal

Eggersgluss S., Miyase K., Wen X.

IEEE European Test Symposium 2016-July 2016.05

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill Reviewed International journal

D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35 ( 3 ) 499 - 512 2016.03

Test Pattern Modification for Average IR-Drop Reduction Reviewed International journal

W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen

IEEE Transactions on VLSI Systems 24 ( 1 ) 38 - 49 2016.01

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch Reviewed International journal

IEEE Asian Test Symposium 103 - 108 2015.11

Power Supply Noise and Its Reduction in At-Speed Scan Testing Invited Reviewed International journal

X. Wen

IEEE International Conference on ASIC Paper B5-3 2015.11

Authorship：Lead author,　Last author,　Corresponding author Language：English Publishing type：Research paper (international conference proceedings)

China Chengdu 2015.11.03 - 2015.11.06

DOI： 10.1109/ASICON.2015.7516980

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84982256034&origin=inward

A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys Reviewed International journal

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

24th International Workshop on Logic and Synthesis 2015.06

Identification of High Power Consuming Areas with Gate Type and Logic Level Information Reviewed International journal

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE European Test Symposium Paper 9.1 2015.05

A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys Reviewed International journal

IEEE European Test Symposium Poster 2.4 2015.05

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Papers - WEN Xiaoqing